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[Other resource] fir-vhdl

Description: 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Description Languages in preparing the FIR digital filter
Platform: | Size: 5335 | Author: MAX | Hits:

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[VHDL-FPGA-Verilog] FPGA_FIR

Description: VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
Platform: | Size: 152576 | Author: 冯申 | Hits:

[Communication-Mobile] 2005612300003FIRVHDL

Description: 自己在一个通信项目中设计的滤波器，在传统设计的基础上作了改进，具有更好的特性。-himself in a communications projects designed filter, in the traditional design made on the basis of improvement has better features.
Platform: | Size: 26624 | Author: 小令 | Hits:

[VHDL-FPGA-Verilog] fir-vhdl

Description: 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Description Languages in preparing the FIR digital filter
Platform: | Size: 5120 | Author: MAX | Hits:

[VHDL-FPGA-Verilog] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Platform: | Size: 909312 | Author: 王志 | Hits:

[VHDL-FPGA-Verilog] fir_Verilog

Description: 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
Platform: | Size: 5120 | Author: yuming | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Platform: | Size: 12288 | Author: 田文军 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: FIR滤波器的性能参数 设计一个滤波器最基本的就是性能参数的,决定着滤波器的实际功能.比如阶数,截至频率。 本文滤波器设计参数 ①输入,输出数据宽度10位 ②阶数为4阶的线性相位FIR滤波器， ③类型:带通 -FIR filter performance parameters The design of a filter is the most basic performance parameters, determines the actual filter function. For example, the order, as the frequency. In this paper, filter design parameters ① input and output data width of 10 ② order for the 4 order of the linear phase FIR filter, ③ Type: Band Pass
Platform: | Size: 3072 | Author: bobo | Hits:

[VHDL-FPGA-Verilog] fir

Description: Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
Platform: | Size: 1024 | Author: lifei | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[VHDL-FPGA-Verilog] VHDLonfir

Description: FIR滤波器在VHDL中使用(顺序)PROCESS声明或者是加法器和乘法器的“组件 实例”来实现-FIR filter in VHDL use (in order) PROCESS statement or the adder and the multiplier " component instance" to achieve the
Platform: | Size: 1024 | Author: wangYC | Hits:

[Software Engineering] wrwar

Description: EE367 Lab 6 Creating a FIR filter in VHDL
Platform: | Size: 1238016 | Author: Karama | Hits:

[Other] fir

Description: 是一个fir滤波器 其中使用了MAC单元去实现累加和乘法运算。-A fir filter which uses the MAC unit to achieve accumulation and multiplication.
Platform: | Size: 1024 | Author: 张晓东 | Hits:

[VHDL-FPGA-Verilog] firfilterr

Description: this is a coding file for FIR filter in vhdl
Platform: | Size: 2048 | Author: rakhi | Hits:

[VHDL-FPGA-Verilog] 20FIRfilterwithCSD

Description: 20阶FIR滤波器，用CSD编码对参数进行了设计-20-order FIR filter with CSD coding of the design parameters
Platform: | Size: 3072 | Author: zhuhui | Hits:

[VHDL-FPGA-Verilog] FIR-FILTER

Description: FIR filter LUT based in vhdl
Platform: | Size: 217088 | Author: sat | Hits:

[VHDL-FPGA-Verilog] Low-Power-FIR-Filter

Description: FIR滤波在数字信号领域中很大作用。这个源码很大帮助VHDL工程师或学习者。里面包含说明书。-This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.
Platform: | Size: 437248 | Author: 金铁男 | Hits:

[Other] VHDL-FIR-filters

Description: ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has been synthesized with Xilinx Vivado 2015.1 to confirm the correct DSP cascade chain is inferred.
Platform: | Size: 37888 | Author: Abkoti | Hits:
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